This invention relates to large scale integration (LSI) circuit chips and very large scale integration (VLSI) circuit chips, and more particularly to LSI and VLSI circuit chips using complementary metal oxide semiconductor (CMOS) logic circuitry. Still more particularly, the present invention relates to CMOS LSI and VLSI circuit chips including a special set of integral test circuitry which, in addition to being used to functionally test the chip, is used to test the electrical delay of the circuits on the chip prior to packaging in an integrated circuit package.
Integrated circuit chips are formed on a wafer. A wafer is a thin slice of pure silicon, typically four inches in diameter for LSI and VLSI circuits, on which an array of chips are fabricated. The wafer is scribed, along the unused channels between the chips, and the chips are broken off from the wafer. They are then packaged in an integrated circuit package for testing and, if they pass testing, for use.
The percentage of properly operating chips on a wafer, i.e., the yield, is often very low. In LSI and VLSI technology, the yield can be as low as 10 percent because of the complexities involved in the fabrication process. Since the packaging of a chip adds considerably to its manufacturing cost, it is desirable to fully test chips when they are still part of the wafer to avoid the expense of packaging defective chips.
There are typically three types of tests that are required to fully test an integrated circuit: (1) functional tests show whether all the circuits function as required; (2) parametric tests show that the input and output circuits of the chip have the correct electrical characteristics; and (3) delay tests show that the circuits perform with the necessary speed. This invention provides a means of easily performing the third test while the CMOS LSI or VLSI chip is still part of the wafer.
Delay testing of CMOS LSI or VLSI chips has not heretofore been possible for the reasons set forth below. However, it will be helpful to understand the advantages of the present invention to review the evolution of delay testing as it relates to non-LSI or -VLSI integrated circuit technology.
Testing chips when they are part of the wafer requires a method of getting signals into, and readings signals from, the chip's input/output (I/O) pads. Probe mechanisms have been developed to satisfy this need. A probe is a mechanical arm, electrically conductive, with a fine point on one end to make electrical contact with an I/O pad; the other end of the probe being wired to the tester electronics. Probe systems have been fabricated that have as many probes as the number of I/O pads on the chip being tested. The contact ends of the probes are arranged in the same pattern as the I/O pads such that when the chip is aligned under the probes, an electrical signal from the tester causes the probe points to lower and make contact with the I/O pads.
When contact is made with all the I/O pads, test patterns can be applied to the input pads and a clock signal, if necessary, is generated by the tester and sent to the appropriate input pad. The response of the circuitry on the chip to the input signals can then be read by the tester through the probes connected to the output pads. The tester can compare the output pattern read from the chip to the pattern that is expected, based upon the input pattern, and determine if the chip is functioning correctly. Thus, the probe system satisfies the functional test requirement of testing chips while still part of the wafer.
The probe system is also used for delay measurements by the use of special test chips. These test chips are placed at strategic locations within the array of desired functional chips, thereby using up space on the wafer that could otherwise be used for additional functional chips. The test chips have a small number of I/O pads and the delay test is performed using a probe mechanism that is different from that used for functional test of the other chips. Because of the small number of I/O pads on the test chip, the probe arms on the delay tester can be made very small. Therefore, the inductance of the probe arms does not affect the delay test results. Since each test chip displaces a potentially usable functional chip, only a small number of test chips are used on each wafer.
The results of delay testing test chips (which results may vary by as much as 25 percent) can be used to reject an entire wafer. However, even if the delay test results do not cause wafer rejection, all the functional chips that passed functional test must still be delay tested after being individually packaged. As explained below, as the density of integrated circuit technology increased, the use of these test chips became impractical.
In the early 1970's, wafers were typically 2-inches in diameter and the line widths (the minimum dimension) on a chip were typically 7-microns. The mask (a different mask is required for each step in the wafer fabrication process) was typically 1:1 size and was used to expose the resist on the wafer using a contact printing process. The mask was generated using a reticle, which was the pattern for one layer of one chip. The original layout was made using manual or automated techniques and was usually much larger than actual size; typically 100:1 to 500:1. This was reduced, using photographic reduction methods, to the reticle which was typically a 10:1 size. The reticle was then inserted into a step-and-repeat camera which reduced it to a 1:1 size, as it exposed the pattern on the mask. The mask locations that were to have the test chip pattern were skipped. When all of the chip pattterns were exposed on the mask, the test chip reticle was inserted in the step-and-repeat camera and the camera exposed the test chip pattern in the blank locations.
By the mid-1970's, wafers were typically 3-inches in diameter and line widths on a chip were typically 4-microns. The mask was generated at a 1:1 size, including the test chips, by electron-beam systems, and exposed on the wafer by a 1:1 projection alignment system.
By 1980, wafers were typically 4-inches in diameter and line widths on a chip were typically 2-microns. The projection alignment system was no longer adequate for the accuracy required. Because of the small dimensions involved, reticles were generated at 10:1 size using an electron beam system. Masks were not used; rather the reticle was exposed on the wafer resist using a direct step on wafer (DSW) system. The DSW system did not allow the replacement of the chip reticle with a test chip reticle because of the very fine tolerances involved in making the exposure. Thus, by the time VLSI technology had emerged, test chips were no longer practical.
Performing delay tests on a normal chip in LSI and VLSI technology has not heretofore been practical for two major reasons: (1)circuit delays decreased; and (2) the number of I/O pads increased as LSI and VLSI technology developed.
The decrease in circuit delays means that the time between the application of the input pulses and the detection of the output pulse becomes smaller, dictating a more precise measurement of the time involved if the answers are to be meaningful. As the circuit density of the chip and the number of I/O pads increased, the size of the chip did not increase in the same proportion. In fact, as the number of I/O pads on a chip increased, they had to be made smaller and closer together.
The end of the probe arm which is wired to the tester is much wider than the contact end. Therefore, the row of probe arms along each side of a chip form a "fan", narrow at the probe end and wide at the end wired to the tester. Since a chip is typically square, with I/O pads and probe arms along each side, as the number of I/O pads increased, the length of the probe arm has to increase because the four "fans" get wider at the tester end of the probe arm. This increased probe length adds significant inductance to the test circuits used for delay testing.
As mentioned above, the decreased circuit delays inherent to LSI and VLSI technology require more precise measurement when performing delay tests. This means that the rise and fall times of the signals generated and measured must be small compared to the delay being measured. Further, the switching point of the output signal, with respect to the switching point of the input signal, must be measured more accurately. However, the inductance of the longer probe distorts the signals used for the delay test, lenthening the otherwise fast rise or fall times. Thus, even though a delay can be measured, the time between the switchings of the first input circuit and last output circuit can not be determined with enough accuracy to make a go/no-go decision. Therefore, LSI and VLSI chips, while still part of the wafer, are functionally tested, but accurate delay testing must still be done after the chip is packaged in an integrated circuit package.